The present invention relates to a semiconductor memory device, and more particularly, to a circuit and a method for resetting a pair of data buses.
FIG. 1 is a schematic diagram of a part of a conventional semiconductor memory device 1 comprising a memory cell array 4 including a plurality of memory cells c, a plurality of word lines (not shown) and a plurality of bit line pairs BL1, /BL1 to BLn, /BLn. Each cell c is connected to one of the plurality word lines and also to one of bit lines of any pair BL1, /BL1 to BLn, /BLn. Only three pairs of bit lines, designated as first, second and third line pairs BL1, /BL1; BL2, /BL2; and BL3, /BL3 are shown in FIG. 1.
Sense amps 2a, 2b and 2c are connected between the first, second and third bit line pairs BL1, /BL1; B12, /BL2; and BL3, /BL3, respectively. Each of the sense amps 2a to 2c amplifies a potential difference between the associated one of the first, second and third bit line pairs BL1, /BL1 to BL3, /BL3. The bit lines pairs BL1 to BL3 and /BL1 to /BL3 are also connected to a pair of data buses DB, /DB via pairs of transfer gates 3a to 3c, respectively. Each pair of transfer gates 3a to 3c includes a pair of NMOS transistors having gates which receive a common column select signal col 1 to col3. When the column select signal col 1, for example, goes high, the transfer gates 3a are turned on, thus electrically connecting the first bit line pair BL1, /BL1 to the data buses DB, /DB.
In a write operation, write data from a write amplifier is written in the memory cell c via the data buses DB, /DB, the transfer gates 3a and the first bit line pair BL1, /BL1. In a read operation, data stored in the memory cell c is read via the first bit line pair, BL, /BL1, the transfer gates 3a and the data buses DB, /DB to a read amplifier (not shown).
A reset circuit 50 (60) is connected between the data buses DB, /DB. The reset circuit 50 of a first prior art example is shown in FIG. 2(a) and the reset circuit 60 of a second prior art example is shown in FIG. 3(a). Each reset circuit 50 or 60 receives a reset control signal .phi.eq which transitions in the manners illustrated in FIG. 2(b) and 3 (b). The reset circuit 50 or 60 resets the potential difference between the data buses DB, /DB in response to the high reset control signal .phi.eq applied subsequent to a write operation or a read operation.
As shown in FIG. 2(a), the reset circuit 50 comprises three NMOS transistors Q51, Q52 and Q53. The NMOS transistor Q51 is connected between the data buses DB, /DB, and the NMOS transistors Q52 and Q53 are connected in series between the data buses DB, /DB. A precharge voltage equal to about half of a high potential power supply Vdd (i.e., Vdd/2) is applied to a node between the NMOS transistors Q52 and Q53. The transistors Q51 to Q53 have their gates connected together and receive the reset control signal .phi.eq.
When the NMOS transistors Q51 to Q53 are turned on in response to the high reset control signal .phi.eq, the potentials on the data buses DB, /DB are equalized to Vdd/2 as illustrated in FIG. 2(b), thus resetting the potential difference between the data buses DB, /DB. By the Vdd/2 equalization, a power consumption of the reset circuit 50 is reduced.
As shown in FIG. 3(a), the reset circuit 60 comprises an NMOS transistor Q61, two PMOS transistors Q62 and Q63 and an inverter circuit 61. The NMOS transistor Q61 is connected between the data buses DB, /DB, and the PMOS transistors Q62 and Q63 are connected in series between the data buses DB, /DB. A precharge voltage having a level equal to a high potential power supply Vdd is applied to a node between the transistors Q62 and Q63. A reset control signal .phi.eq is applied to the gate of the transistor Q61. The reset control signal .phi.eq inverted by the inverter circuit 61 is applied to the gates of the PMOS transistors Q62 and Q63.
When the NMOS transistor Q61 and the PMOS transistors Q62 and Q63 are turned on in response to the high reset control signal .phi.eq, the potentials on the data buses DB, /DB are equalized to the high potential power supply level Vdd as illustrated in FIG. 3(b), thus resetting the potential difference between the data buses DB, /DB. Accordingly, if the next cycle is a read cycle, a difference between the potential on any bit line BL1, /BL1 to BL3, /BL3 corresponding to data read from the memory cell c and the potential on the data bus DB or /DB will increase to the supply Vdd level. This improves the charge transfer rate through the associated transfer gate 3a to 3c and reduces the time t1 required until the potential on the data bus DB or /DB is determined. Thus, the read operation is accelerated in the semiconductor memory device 1 using the reset circuit 60.
Since the reset circuit 50 equalizes the potentials on the data buses DB, /DB to the Vdd/2 during the reset operation, a read operation is slow. During the read operation, there is a small difference (Vdd/2) between the potential on any of the first to the third bit line BL1, /BL1 to BL3, / BL3 corresponding to data read from the memory cell c and the potential on the data bus DB or /DB. This slows down the charge transfer rate through the transfer gate 3a to 3c, resulting in a relatively long time t2 until the potential on the data buses DB, /DB is determined, as illustrated in FIG. 2(b).
Since the reset equalizes the potentials on the data buses DB, /DB to Vdd level during the reset operation, power consumption is increased. A write amplifier generally has a greater driving capability than the sense amps 2a to 2c in order to facilitate the charge/discharge process of the data buses and the first to the third bit line pair. An increased power consumption accrues during the reset operation of the write cycle when equalizing the data buses to the Vdd level.